I’m taking a module called Digital Systems Synthesis this semester which covers some of the algorithms used by modern high level synthesis tools to generate RTL code. Our lecturer told us about a coursework he used to set where we were expected to write a very basic high level synthesis tool; he stopped setting it a few years back because he thought it was too programming oriented. It sounds like a pretty awesome side-project so I’ve decided to give it a go!

I’m not sure how long it’ll take me to complete so I’ve decided to split my progress over multiple blog posts. I’ll start by briefly describing what high level synthesis actually is and what elements I’m expecting my simple program to have.

Digital Design Flow

Chip design is immensely difficult because we can fit so many transistors in them (around 30 million on a pin head!) so we can’t think of it as a single design. It is broken up into many smaller modules that are designed under various “levels of abstraction” which basically means a set of interdependent tasks.

The figure above shows the process used for digital chip design and it may be surprising just how far removed the physical transistors are. There are so many in modern designs that it just becomes impractical to consider each one. Hardware Description Languages (like Verilog, VHDL and SystemC) are used for every level apart from the physical layout and look very similar to programming languages but there is a difference that will become apparent later.

You may be wondering if this means that modern chips are actually designed by programs. Well they certainly play a very large part in a lot of widespread designs. Hardware description language (HDL) code is fed into compilers in exactly the same way that programming language code is, but there is a specialist compiler for each dashed line in the figure. High level synthesis tools produce RTL, RTL compilers produce netlists, and layout tools produce silicon layouts. It does take care and skill to drive these tools effectively and often some hand tweaking may be required to make the most of the design, but ultimately this is how it all works.

I’m going to focus on the thing at the very top. I’m planning to make a very basic HDL that is capable of describing equations and algorithms, and then feed that into SimpleHLST which will generate Verilog code. In an ideal situation I would synthesise the output of this onto an FPGA but that is a long way off just yet.

The Plan

There is a lot to consider for this project, and I think the tasks will break down as follows.

  • Read in language and generate data flow graph (DFG)
  • Run ASAP/ALAP algorithms on the DFG to work out what functional units are required
  • Use constrained algorithms on the DFG to get an optimal design for our purpose
  • Join the functional units together using data-path synthesis techniques
  • Finally, synthesise a controller to drive the data-path

After this lengthy process SimpleHLST should produce some Verilog code that we can simulate to make sure it works.

Onwards!

In the next part we’ll design a very basic HDL that will fit our needs and, hopefully, start a program that may even understand it!